Space and time compaction schemes for embedded cores

Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os. The trade-off between test application time, test bandwidth and area overhead should be exploited since it imposes certain restrictions on the Test Access Mechanism to be implemented. We outline an aliasing-free space and time compaction scheme, for both combinational and sequential cores, which minimizes the required test bandwidth and reduces the test bandwidth consumption at the core output side. The experimental results show that the test bandwidth gain is achieved with almost no increase in test application time.